FPLD Implementation of Computation over Finite Fields GF(2m) with Applications to Error Control Coding
نویسنده
چکیده
This paper investigates the implementation of computations over nite elds GF(2 m) using eld-programmable logic devices (FPLDs). Implementation details for addition/subtraction, multiplication , square, inversion, and division are given with mapping results for Xilinx LCAs, Altera CPLDs and Actel ACT FPGAs. As an application example, mapping results for complete encoders for error-correcting codes are also presented. Finally, new opportunities emerging from FPLD technology for data transmission systems with dynamic code adaption are discussed.
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تاریخ انتشار 1995